Friday, February 29, 2008

My VHDL lab. Cadence, Simple starter examples

I have used program like Max Plus, Quartus, XILINX ISE, Modelsim but none of them had such a bad interface like Cadence Nclaunch. The interface really sucks. Beside that, it is one of the best packets in the market.

Below are 2 simple exercises i had to do with
Cadence Nclaunch.

Exercise 1: Write a VHDL file and a test bench for a comparator circuit. The input ports
are std_logic_vectors (1 downto 0) A and B and the output ports are std_logic signals: less, equal and greater. The circuits compares the vectors A and B. If A is less than B, then less is assigned value 1 and the rest of the output ports are assigned value 0 and so on.

VHDL code

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity exc1 is
Port (A, B : in STD_LOGIC_VECTOR (1 downto 0);
less, greater, equal: out STD_LOGIC);
end exc1;

architecture Behavioral of exc1 is

signal less1, greater1, equal1 : STD_LOGIC;

begin

process(A, B, less1, greater1, equal1)
begin
if (A >B) then
less1 <= '0'; greater1 <= '1'; equal1 <='0'; elsif(A=B) then less1 <= '0'; greater1 <= 0'; equal1 <='1'; else less1 <= '1'; greater1 <= '0'; equal1 <='0'; end if; end process; less<=less1; greater<=greater1; equal<=equal1; end Behavioral;

Test bench


library IEEE;
use IEEE.std_logic_1164.all;

entity exc1_test is
end exc1_test;

architecture test of exc1_test is

component exc1
port(A, B : in STD_LOGIC_VECTOR (1 downto 0);
less, greater, equal: out STD_LOGIC );
end component;

for i1: exc1 use entity work.exc1(behavioral);
signal A, B : STD_LOGIC_VECTOR (1 downto 0);
signal less, greater, equal : std_logic;
begin
i1: exc1 port map( A,B,less, greater, equal);

simulate: process
begin

A<="00"; B<="00"; wait for 10 ns; A<="00"; B<="01"; wait for 10 ns; A<="00"; B<="10"; wait for 10 ns; A<="00"; B<="11"; wait for 10 ns; A<="01"; B<="00"; wait for 10 ns; A<="01"; B<="01"; wait for 10 ns; A<="01"; B<="10"; wait for 10 ns; A<="01"; B<="11"; wait for 10 ns; A<="10"; B<="00"; wait for 10 ns; A<="10"; B<="01"; wait for 10 ns; A<="10"; B<="10"; wait for 10 ns; A<="10"; B<="11"; wait for 10 ns; A<="11"; B<="00"; wait for 10 ns; A<="11"; B<="01"; wait for 10 ns; A<="11"; B<="10"; wait for 10 ns; A<="11"; B<="11"; wait for 10 ns; end process simulate; end test;

Exercise 2: Write a VHDL file and a test bench for a decoder circuit. The input port is a
std_logic_vector (1 downto 0) I and the output port is a std_logic_vector(3 downto 0) Out. The behavior of the circuit is as follows: (Out=0001 when I = 00, Out=0010 when I = 01, Out=0100 when I = 10, Out=1000 when I = 11, otherwise, Out=XXXX) .

VHDL code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity exc2 is
Port ( I : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC_VECTOR (3 downto 0));
end exc2;

architecture Behavioral of exc2 is
signal temp:STD_LOGIC_VECTOR (3 downto 0);
begin

process(I)
begin
if (I="00") then
temp <= "0001"; elsif(I="01") then temp <= "0010"; elsif(I="10") then temp <= "0100"; elsif(I="11") then temp <= "1000"; else temp <= "XXXX"; end if; end process; output <= temp; end Behavioral;

Test bench


library IEEE;
use IEEE.std_logic_1164.all;

entity exc2_test is
end exc2_test;

architecture test of exc2_test is
component exc2
port( I: in STD_LOGIC_VECTOR (1 downto 0);
output: out STD_LOGIC_VECTOR(3 downto 0));
end component;


for i2: exc2 use entity work.exc2(behavioral);

signal I : STD_LOGIC_VECTOR (1 downto 0);
signal output : STD_LOGIC_VECTOR (3 downto 0);

begin

i2: exc2 port map(I, output);

simulate: process
begin

I<="00"; wait for 10 ns;
I<="01"; wait for 10 ns;
I<="10"; wait for 10 ns;
I<="11"; wait for 10 ns;

end process simulate;

end test;

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